add_phase.v 相位累加器
module add_phase (
input wire sys_clk,
input wire sys_rst_n,
output wire [8:0] rom_addr_reg
);
parameter FREQ_CTRL = 32'd85899345;
reg [31:0] fre_add;
always @(posedge sys_clk or negedge sys_rst_n) begin
if(sys_rst_n == 1'b0)
fre_add <= 32'd0;
else
fre_add <= fre_add +FREQ_CTRL;
end
assign rom_addr_reg = fre_add[31:23];
endmodule
comp4.v 四位比较器
module comp4(a, b, lg, eq, sm);
input [3:0] a, b;
output lg, eq, sm;
reg lg, eq, sm;
always @ (a or b)
begin
if (a > b) begin lg <= 1; eq<= 0; sm <= 0; end
if (a == b) begin lg <= 0; eq<= 1; sm <= 0; end
if (a < b) begin lg <= 0; eq<= 0; sm <= 1; end
end
endmodule
cont10_1.v 模10计数器一
module cont10_1(clk, y, cout);
input clk;
output [3:0] y;
output cout;
reg[3:0] y;
reg cout;
always @(posedge clk)
begin
if (y<9)
begin
y <= y+1;
cout <= 0;
end
else
begin
y <= 0;
cout <= 1;
end
end
endmodule
cont10_2.v 模10计数器二
module cont10_2 (clk, clr, en, c, q);
input clk, clr, en;
output c, q;
reg c;
reg [3:0] q;
always @(posedge clr or posedge clk)
if (clr) q <= 0;
else if (en)
if (q == 9) begin q <= 0; c <= 1; end
else begin q <= q + 1; c <= 0; end
endmodule
cont8.v 模8计数器
module cont8 (clk, y);
input clk;
output [2:0] y;
reg [2:0] y;
always @(posedge clk)
begin
y <= y + 1;
end
endmodule
d_ff.v 带使能D触发器
module d_ff(en, d, clk, q, nq);
input en, d, clk;
output q, nq;
reg q;
wire nq;
always @(posedge clk)
begin
if (en == 1) q <= d;
else q <= 0;
end
assign nq = !q;
endmodule
dff8.v 串入并出移位寄存器
module dff8(din, clk, q);
input din, clk;
output [7:0] q;
reg [7:0] q;
always @(posedge clk)
begin
q[7] <= din;
q[6:0] <= q[7:1];
end
endmodule
dtsm.v 数码管动态扫描
module dtsm(clk, dai0, dai1, dai2, dai3, dai4, dai5, dai6, dai7, wx, dm);
input clk;
input [3:0] dai0, dai1, dai2, dai3, dai4, dai5, dai6, dai7;
output [7:0] dm;
output [7:0] wx;
reg [7:0] dm;
reg [7:0] wx;
reg [2:0] y;
reg [3:0] dout;
always @(posedge clk)
begin
if (y<7)
y <= y + 1;
else
y <= 0;
end
always @(y) begin
case (y)
3'b000 : begin dout <= dai0; wx <= 8'b11111110; end
3'b001 : begin dout <= dai1; wx <= 8'b11111101; end
3'b010 : begin dout <= dai2; wx <= 8'b11111011; end
3'b011 : begin dout <= dai3; wx <= 8'b11110111; end
3'b100 : begin dout <= dai4; wx <= 8'b11101111; end
3'b101 : begin dout <= dai5; wx <= 8'b11011111; end
3'b110 : begin dout <= dai6; wx <= 8'b10111111; end
3'b111 : begin dout <= dai7; wx <= 8'b01111111; end
endcase
end
always @(dout) begin
case (dout)
4'b0000 : dm <= 8'b00000001;
4'b0001 : dm <= 8'b01001111;
4'b0010 : dm <= 8'b00010010;
4'b0011 : dm <= 8'b00000110;
4'b0100 : dm <= 8'b01001100;
4'b0101 : dm <= 8'b00100100;
4'b0110 : dm <= 8'b00100000;
4'b0111 : dm <= 8'b00001111;
4'b1000 : dm <= 8'b00000000;
4'b1001 : dm <= 8'b00000100;
4'b1010 : dm <= 8'b00001000;
4'b1011 : dm <= 8'b01100000;
4'b1100 : dm <= 8'b00110001;
4'b1101 : dm <= 8'b01000010;
4'b1110 : dm <= 8'b00110000;
4'b1111 : dm <= 8'b00111000;
default : dm <= 8'b01111111;
endcase
end
endmodule
exam138.v 位选译码器
module exam138(in, y);
input [2:0] in;
output [7:0] y;
reg [7:0] y;
always @(in)
begin
case(in)
3'b000 : y <= 8'b11111110;
3'b001 : y <= 8'b11111101;
3'b010 : y <= 8'b11111011;
3'b011 : y <= 8'b11110111;
3'b100 : y <= 8'b11101111;
3'b101 : y <= 8'b11011111;
3'b110 : y <= 8'b10111111;
3'b111 : y <= 8'b01111111;
endcase
end
endmodule
exam38.v 带使能译码器
module exam38 (a, b, c ,y, en);
input a, b, c, en;
output [7:0] y;
reg [7:0] y;
always @(a or b or c or en)
begin
if (en) y <= 8'b11111111;
else
case ({c,b,a})
3'b000: y <= 8'b11111110;
3'b001: y <= 8'b11111101;
3'b010: y <= 8'b11111011;
3'b011: y <= 8'b11110111;
3'b100: y <= 8'b11101111;
3'b101: y <= 8'b11011111;
3'b110: y <= 8'b10111111;
3'b111: y <= 8'b01111111;
endcase
end
endmodule
fp.v 分频控制器
module fp(clk, fout);
input clk;
output fout;
reg[24:0] y;
reg cout, fout;
always @(posedge clk)
begin
if (y<25000000)
begin
y <= y+1;
cout <= 0;
end
else begin
y <= 0;
cout <= 1;
end
end
always @(posedge cout) begin
fout <= !fout;
end
endmodule
qdymq.v 七段译码器一
module qdymq (bin, y);
input [3:0] bin;
output [7:0] y;
reg [7:0] y;
always @(bin)
begin
case (bin)
4'b0000 : y <= 8'b00000011;//0
4'b0001 : y <= 8'b10011111;//1
4'b0010 : y <= 8'b00100101;//2
4'b0011 : y <= 8'b00001101;//3
4'b0100 : y <= 8'b10011001;//4
4'b0101 : y <= 8'b01001001;//5
4'b0110 : y <= 8'b01000001;//6
4'b0111 : y <= 8'b00011111;//7
4'b1000 : y <= 8'b00000001;//8
4'b1001 : y <= 8'b00001001;//9
4'b1010 : y <= 8'b00010001;//A
4'b1011 : y <= 8'b11000001;//B
4'b1100 : y <= 8'b01100011;//C
4'b1101 : y <= 8'b10000101;//D
4'b1110 : y <= 8'b01100001;//E
4'b1111 : y <= 8'b01110001;//F
default : y <= 8'b11111111;
endcase
end
endmodule
reg4.v 四路寄存器
module reg4(set, dain3, daout0, dain2, daout1, dain1, daout2, dain0, daout3);
input set;
input [3:0] dain3, dain2, dain1, dain0;
output [3:0] daout0, daout1, daout2, daout3;
wire set;
reg [3:0] daout0, daout1, daout2, daout3;
always @(posedge set) begin
daout3 <= dain3;
daout2 <= dain2;
daout1 <= dain1;
daout0 <= dain0;
end
endmodule
shft2.v 多模式移位寄存器
module shft2(clk, md, d, qb);
output [7:0] qb;
input clk;
input [7:0] d;
input [7:0] md;
reg [7:0] REG;
always @(posedge clk)
begin
case (md)
0: begin REG[0] <= REG[7]; REG[7:1] <= REG[6:0]; end
1: begin REG[7] <= REG[0]; REG[6:0] <= REG[7:1]; end
2: begin REG <= d; end
default: REG <= REG;
endcase
end
assign qb = REG;
endmodule
slet4.v 四选一选择器
module slet4 (a, b, c, d, s1, s2, y);
input a, b, c, d, s1, s2;
output y;
reg y;
always @(s1 or s2)
begin
case ({s1,s2})
0: y <= a;
1: y <= b;
2: y <= c;
3: y <= d;
endcase
end
endmodule
snot.v 取反门
module snot(b, z);
input b;
output z;
wire z;
assign z = !b;
endmodule
t_cont.v 时序控制生成器
module t_cont(clk_lhz, en, set, clr);
input clk_lhz;
output en, set, clr;
reg en;
wire set, clr;
reg en_temp;
always @(posedge clk_lhz) en <= !en;
always @(negedge clk_lhz) en_temp <= en;
assign set = !en & en_temp;
assign clr = ! (en | en_temp);
endmodule
xzq4w8xl.v 选择输出译码
module xzq4w8xl (sl, dout);
input [2:0] sl;
output [3:0] dout;
reg [3:0] dout;
always @(*) begin
case (sl)
3'b000: dout = 1;
3'b001: dout = 2;
3'b010: dout = 3;
3'b011: dout = 4;
3'b100: dout = 5;
3'b101: dout = 6;
3'b110: dout = 7;
3'b111: dout = 8;
endcase
end
endmodule
ymq.v 七段译码器二
module ymq(bin, y);
input [3:0] bin;
output [7:0] y;
reg [7:0] y;
always @(bin)
begin
case(bin)
4'b0000 : y <= 8'b00000011;//0
4'b0001 : y <= 8'b10011111;//1
4'b0010 : y <= 8'b00100101;//2
4'b0011 : y <= 8'b00001101;//3
4'b0100 : y <= 8'b10011001;//4
4'b0101 : y <= 8'b01001001;//5
4'b0110 : y <= 8'b01000001;//6
4'b0111 : y <= 8'b00011111;//7
4'b1000 : y <= 8'b00000001;//8
4'b1001 : y <= 8'b00001001;//9
4'b1010 : y <= 8'b00010001;//A
4'b1011 : y <= 8'b11000001;//B
4'b1100 : y <= 8'b01100011;//C
4'b1101 : y <= 8'b10000101;//D
4'b1110 : y <= 8'b01100001;//E
4'b1111 : y <= 8'b01110001;//F
default : y <= 8'b11111111;
endcase
end
endmodule
ztj.v 八状态控制器
module ztj(clk,reset,state_in,com_out);
input clk,reset;
input state_in;
output [7:0] com_out;
reg[7:0] com_out;
parameter s0=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6,s7=7;
reg[7:0] c_st,next_st;
always@(posedge clk or negedge reset)
begin
if(!reset) c_st<=s0;
else c_st<=next_st;
end
always@(c_st or state_in)
begin
case(c_st)
s0:begin
com_out<=8'b00000001;
if(state_in==1'b0) next_st<=s1;
else next_st<=s7;
end
s1:begin
com_out<=8'b00000010;
if(state_in==1'b0) next_st<=s2;
else next_st<=s0;
end
s2:begin
com_out<=8'b00000100;
if(state_in==1'b0) next_st<=s3;
else next_st<=s1;
end
s3:begin
com_out<=8'b00001000;
if(state_in==1'b0) next_st<=s4;
else next_st<=s2;
end
s4:begin
com_out<=8'b00010000;
if(state_in==1'b0) next_st<=s5;
else next_st<=s3;
end
s5:begin
com_out<=8'b00100000;
if(state_in==1'b0) next_st<=s6;
else next_st<=s4;
end
s6:begin
com_out<=8'b01000000;
if(state_in==1'b0) next_st<=s7;
else next_st<=s5;
end
s7:begin
com_out<=8'b10000000;
if(state_in==1'b0) next_st<=s0;
else next_st<=s6;
end
default:next_st<=s0;
endcase
end
endmodule
